Computer Engineering @SJSU

Building a local-first agentic AI platform that automates hardware formal verification for RTL teams.

• Designed a 7-agent verification pipeline that generates, critiques, fixes, and refines SystemVerilog Assertions from RTL and plain-English specs.
• Grounded assertion generation with RAG across 120+ curated hardware resources, including IEEE 1800, AMBA/AXI specs, and prior assertion failures.
• Integrated SymbiYosys, Jasper, Questa, and VCS Formal with RCA agents that inspect counterexample VCD traces and rewrite failing properties.
• Built FastAPI and Next.js dashboards for browsing runs, assertions, coverage, RCA reports, benchmarks, and versioned run manifests.
• Improved benchmark results to 100 percent proven rate on sync FIFO few-shot tests and raised Float Multiplier HIL results from 62 percent to 100 percent.

Leading core club operations across infrastructure, frontend coordination, and event execution for the AI & ML community at SJSU.

• Manage Supabase and database infrastructure.
• Collaborate with the UI team on frontend development.
• Plan and organize club events.

Worked on model deployment and data validation workflows to make internal ML systems more reproducible, faster to train, and easier to trust.

• Containerized LLaMA-3 and Mistral models with Docker for reproducible environments.
• Built Pandera-based validation pipelines to enforce schemas and cut runtime data issues before training.
• Used Unsloth to speed up fine-tuning and reduce training cost by more than 40 percent.
• Automated internal analytics reports with Python and Matplotlib, improving turnaround time by 3x.